Adata 4GB DDR3 1333MHz Desktop Ram

Summary:

Backward-compatible to VDD= 1.5V -0.075V
MRS Cycle with address key programs
- CAS Latency (6,7,8,9)
- Burst Length (BL):8 and 4 with Burst Chop(BC)
Bi-directional, differential data strobe (DQS and /DQS)
Differential clock input (CK, /CK) operation
DLL aligns DQ and DQS transition with CK transition
Double-data-rate architecture; two data transfers per clock cycle
8 independent internal bank
Internal (self) calibration: Internal self calibration through ZQ pin (RZQ:240 ohm±1pecent)
Auto refresh and self refresh
Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C TCASE ≤ 95°C 8-bit pre-fetch.
On Die Termination using ODT pin.
On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM.
EEPROM software write protect.
Lead-free products are RoHS Compliant